High level profiling based low power synthesis technique

We present a prooling based technique for power estimation. This technique is implemented in the pdss (Proole Driven Synthesis System) for the synthesis of low power designs. Initially, each module in the module library is characterized for the average switching capacitance per input vector. The input description is simulated using user-speciied set of input vectors to collect the proole data for various operators and carriers. The proole data, in conjunction with the pre-characterized module library is used to estimate the total capacitance switched by each of the valid schedules produced by the pdssmbox mbox scheduler. A valid schedule is one which satisses other constaints such as area and delay. The schedule with the least switching capacitance estimate is further synthesized to the layout level. Results show an average deviation of 12% compared with the actual switching capacitance values at the layout level.